Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, to increase its speed, and to reduce its power dissipation. However, not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence area, speed and power consumption of the synthesized circuit.

The Impact of Cell Library Characteristics on Area, Speed, and Power Consumption of CMOS Circuits / Macii, Enrico; Poncino, Massimo. - In: INTERNATIONAL JOURNAL OF ELECTRONICS. - ISSN 0020-7217. - 78:(1995), pp. 395-407. [10.1080/00207219508926171]

The Impact of Cell Library Characteristics on Area, Speed, and Power Consumption of CMOS Circuits

MACII, Enrico;PONCINO, MASSIMO
1995

Abstract

Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, to increase its speed, and to reduce its power dissipation. However, not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence area, speed and power consumption of the synthesized circuit.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1705945
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