For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints.

Mapping interleaving laws to parallel turbo decoder architectures / Tarable, Alberto; Benedetto, Sergio. - In: IEEE COMMUNICATIONS LETTERS. - ISSN 1089-7798. - 8:3(2004), pp. 162-164. [10.1109/lcomm.2004.823364]

Mapping interleaving laws to parallel turbo decoder architectures

TARABLE, ALBERTO;BENEDETTO, Sergio
2004

Abstract

For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1534111
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