Archivio Istituzionale della RicercaA new architecture is presented for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated, and the subsequent tradeoff is presented. The proposed architecture is also extended in order to consider other implementations
Reducing Iteration Time When Result Digit isZero for Radix-2 SRT Division and Square Root with Redundant Remainders / Montuschi, Paolo; Ciminiera, Luigi. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - STAMPA. - c-42:2(1993), pp. 239-246. [10.1109/12.204797]
Reducing Iteration Time When Result Digit isZero for Radix-2 SRT Division and Square Root with Redundant Remainders
MONTUSCHI, PAOLO;CIMINIERA, Luigi
1993
Abstract
A new architecture is presented for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated, and the subsequent tradeoff is presented. The proposed architecture is also extended in order to consider other implementations
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https://hdl.handle.net/11583/1402786
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