In a previous paper by P. Montuschi and L. Ciminiera (ibid., vol. 42, no.2 p239-246, Feb 1993), an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work
A Remark on `Reducing Iteration Time WhenResult Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders' / MONTUSCHI P.; CIMINIERA L.. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - STAMPA. - c-44:1(1995), pp. 144-146.
|Titolo:||A Remark on `Reducing Iteration Time WhenResult Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders'|
|Data di pubblicazione:||1995|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/12.368000|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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