This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-Gates) that can be 'frozen' by asserting a control signal. A frozen gate cannot propagate glitches to its output. Algorithms for gate selection and clustering that maximize the percentage of filtered glitches and reduce the overhead for generating the control signals are introduced. A power-efficient CMOS implementation of F-Gates is also described. An important feature of the proposed method is that it can be applied in place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.
|Titolo:||Glitch power minimization by selective gate freezing|
|Data di pubblicazione:||2000|
|Digital Object Identifier (DOI):||10.1109/92.845895|
|Appare nelle tipologie:||1.1 Articolo in rivista|