Recent results have shown that dynamic power management is effective in reducing the total power consumption of sequential circuits. In this paper, we propose a bottom-up approach for the automatic extraction and synthesis of dynamic power management circuitry starting from structural logic-level specifications. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to detect idle conditions where the clock can be stopped without compromising functional correctness. Moreover, symbolic techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 34% have been obtained on standard benchmark circuits.
|Titolo:||Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers|
|Data di pubblicazione:||1999|
|Digital Object Identifier (DOI):||10.1145/323480.323482|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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