This article presents HACRE, a system for recognizing handwritten amounts on checks, which integrates neural networkalgorithmswith context analysis techniques. In particular, HACRE consists of two major subsystems which are strictly interacting: the former is based on an ensemble of neural networks and carries out a kind of pre-recognition of the individual characters, which is by necessity only approximate; the latter is based on a context analysis module which carries out a lexical analysis of the recognized characters, based on a mutual correlation between the legal and courtesy amounts, which must match exactly. This analysis produces hypotheses which correct the errors made by the neural networks. The proposed system is implemented on an ad-hoc VLSI chip containing an array of dedicated processors tailored to the application, and tightly interconnected to a host personal computer.
Mixing Neural Networks and Contextual Analysis in a High-Speed Handwriting Recognizer / Lazzerini, B.; Reyneri, Leonardo; Gregoretti, Francesco; Mariani, M.. - In: INTERNATIONAL JOURNAL OF KNOWLEDGE-BASED AND INTELLIGENT ENGINEERING SYSTEMS. - ISSN 1327-2314. - 2:(1998), pp. 164-177.
Mixing Neural Networks and Contextual Analysis in a High-Speed Handwriting Recognizer
REYNERI, Leonardo;GREGORETTI, Francesco;
1998
Abstract
This article presents HACRE, a system for recognizing handwritten amounts on checks, which integrates neural networkalgorithmswith context analysis techniques. In particular, HACRE consists of two major subsystems which are strictly interacting: the former is based on an ensemble of neural networks and carries out a kind of pre-recognition of the individual characters, which is by necessity only approximate; the latter is based on a context analysis module which carries out a lexical analysis of the recognized characters, based on a mutual correlation between the legal and courtesy amounts, which must match exactly. This analysis produces hypotheses which correct the errors made by the neural networks. The proposed system is implemented on an ad-hoc VLSI chip containing an array of dedicated processors tailored to the application, and tightly interconnected to a host personal computer.Pubblicazioni consigliate
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https://hdl.handle.net/11583/1401089
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