Sfoglia per Autore
Logic Synthesis for Interpolant Circuit Compaction
2019 Cabodi, G.; Camurati, P. E.; Palena, M.; Pasini, P.; Vendraminetto, D.
Schema-Based Instruction with Enumerative Combinatorics and Recursion to Develop Computer Engineering Students' Problem-Solving Skills
2020 Cabodi, G; Camurati, P; Pasini, P; Patti, D; Vendraminetto, D
Citazione | Data di pubblicazione | Autori | File |
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Logic Synthesis for Interpolant Circuit Compaction / Cabodi, G.; Camurati, P. E.; Palena, M.; Pasini, P.; Vendraminetto, D.. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - STAMPA. - 38:2(2019), pp. 380-384. [10.1109/TCAD.2018.2808229] | 1-gen-2019 | Cabodi, G.Camurati, P. E.Palena, M.Pasini, P.Vendraminetto, D. | 08299440.pdf |
Schema-Based Instruction with Enumerative Combinatorics and Recursion to Develop Computer Engineering Students' Problem-Solving Skills / Cabodi, G; Camurati, P; Pasini, P; Patti, D; Vendraminetto, D. - In: INTERNATIONAL JOURNAL OF ENGINEERING EDUCATION. - ISSN 0949-149X. - 36:5(2020), pp. 1505-1528. | 1-gen-2020 | Cabodi, GCamurati, PPasini, PPatti, DVendraminetto, D | ijee2020_SchemaBased.pdf |
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