Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level

Nanostructure based devices are very promising candidates for the emerging nanotechnologies with advantage in terms of power consumption and functional density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor (SET) are the focus of this work. The serious challenges faced by the MOSFET due to scaling limits can be solved by these devices. NWFET provides better gate control and overcomes the short channel effects. SET operates in the quantum confinement regime where the basic operation of MOSFET becomes a challenge. SET works better when the dimensions are small encouraging the process of scaling down. Because of these characteristics of the nanodevices, they have achieved a huge interest from the viewpoint of theoretical as well as applied electronics. The studies focus on the understanding of the basic transport characteristics of the devices. The necessity is to develop a model which is efficient, can be used at circuit level and also provides physical insights of the device. The first part of this work focuses on developing the model for SET and to implement it at the circuit level. The transport properties of SET are studied through quantum simulations. The behavioral characterization of the device is performed and the effect of different device parameters on the transport is studied. Furthermore, the impact of gate voltage is analyzed which modulates the current by shifting the energy levels of the device. After observing the transport through SET, a model is developed that efficiently evaluates the IV characteristics of the device. The quantum simulations are used as reference and a huge computational over-head is achieved while maintaining accuracy. Then the model is implemented in hardware descriptive language showing its functional variability at circuit level by designing some logic circuits like AND, OR and FA. In the second part, the performance of the nanoarrays based on NWFET is characterized. A device level model is developed to evaluate the gate capacitance and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices in nanoarray. A nanoarray implementation for bio-sequence alignment based on a systolic array is realized and its essential performance is evaluated. The power consumption, area and performance of the nanoarray implementation are compared with CMOS implementation. A wide solution space can be explored to find the optimal solution trading power and performance and considering the technological limitations of a realistic implementation.