TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies

We presented here a web-based tool, named TAMTAMS that can accurately calculate the IV characteristics of a transistor based technology and estimate the performance evaluation at system level. We have shown how the modular structure of the tool, makes it possible to estimate an electrical quantity, let’s say A, and evaluate further electrical quantities depending on A in a single run of processing. The tree structure and dependence tree enables a user do analysis from a single nano-scale transistor to a system containing hundreds of thousands of transistors. TAMTAMS Web, as a tool, enables the technologist to observe the effect of changes in process parameters (such as doping Nd)at system level. In other words, the changes in device parameters like Vth, Ion, Ioff etc are reflected in changes in system level performance parameters like Static and Dynamic power consumption. We started the development of the tool from BULK transistor technology by translating the physics based mathematical models as Octave scripts. Moving towards more complex structures like SOI, FinFET, Gate-All-Around, Double/Triple Gate transistors and Post-Silicon technologies like Graphene and Molecular transistors. The technology files (physical parameters)are derived from ITRS roadmap. Transistor models for electrical quantities such as drive current Ion, Off-state current Ioff, Gate leakage current Igate, Threshold voltage Vth etc are integrated inside TAMTAMS. We have shown in our results the tunnelling effect in a transistor i-e how change in Oxide thickness Tox , using parametric analysis, affects gate leakage current Igate . This highlights the intensive nature of the analysis performed with TAMTAMS web. We have shown in our results how static and dynamic power consumption of a Vertex 4 FPGA can be compared for BULK, SOI, DG, GAA and molecular transistor-based technologies. This highlights the extensive nature of the analysis performed with the TAMTAMS Web tool. For interconnection and gate level analysis, NAND and NOR are incorporated inside TAMTAMS as universal gates. Different capacitance models are defined and integrated that acts as bridge between transistors based technologies and system level modules like FPGA, Adders, Multipliers, Memories etc. The tool enables Performance estimation at gate level as well e.g we have shown how reliability models predict the increase in Static/Dynamic power consumption and Delay time for NAND/NOR based circuits. TAMTAMS can be used to analyse different applications under many scenarios. For example, at interconnection level, electromigration models enable the comparison of electromigration effect in copper and Aluminium material based interconnection wires. At system level, different system level modules are written and integrated inside TAMTAMS. For example FPGA module, different types of Adder modules, Multipliers, Content Addressable Memory (CAM), Static RAM (SRAM), Arithmetic and Logic unit (ALU), Finite impulse response filters (FIR) etc. We have shown in the analysis, how a static/dynamic power consumption of an Adder and CAM circuit are affected taking reliability issues into consideration using different technologies. Also in the system level analysis, we have compared performance analysis for Virtex 4 FPGA CLB using current and emerging transistor technologies. Time and space does not allow us to discuss all the technologies and all the integrated modules as it is beyond the scope of this work, but we have analysed few interesting case studies in the analysis part. Regarding the development of the tool TAMTAMS Web, we conclude we have achieved enough and have come a long way considering from where we started, but it is still an on-going work as the technology further evolves. Further we conclude that the tool TAMTAMS Web, as presented in this work, can prove vital for i) technologists in analysis of the process variations ii) for designers to evaluate their circuit design at each of the three levels of abstraction, iii) for transistor model developers to benchmark their proposed models with other industry standard models and iv) for the futurists to know what can be predicted in the years to come regarding transistor based circuit.