During the last years, the increasing popularity of very high resolution formats and the growing of video applications have posed critical issues on both the coding efficiency and the complexity of video compression systems. This thesis focuses on the transform coding stage of the most recent video coding technologies, by addressing both the complexity evaluation and the design of custom hardware architectures. First, the thesis thoroughly analyzes the HEVC transform complexity, by relying on the proposed CI metric. A tool-by-tool investigation is performed to quantify the complexity of the transform stage as function of different coding options, thus identifying which parameters are mainly related to the quality-complexity trade-off. The analysis is concluded with the determination of the transform stage requirements for real life HEVC encoders working in real-time. The obtained results motivate the need of transform hardware architectures. Therefore, an exploration of alternative solutions for hardware architectures to compute the transforms required by the standard is provided. Different DCT and DST factorizations and approximations have been compared in terms of arithmetic cost and sharing degree between multiple transform sizes in order to select the best promising ones for hardware implementation. Then, 1D and 2D transform architectures are proposed and their performance are evaluated within HEVC. The rate-distortion analysis and the hardware synthesis show that the proposed DCT and DST architectures achieve significant area and power reduction with respect to the state-of-art implementations at the expense of very small coding efficiency loss. Finally, this thesis investigates some adaptive transform coding techniques for beyond HEVC video compression, which try to represent the signal with a more sparse representation. The first technique employs odd type sinusoidal transforms. Therefore, some relationships for odd type DCTs and DSTs are recalled and exploited to reuse known factorizations of the DCT-VI and DST-VII to obtain other odd type transforms by applying simple permutations and sign inversions. Low-complexity DCT-V and DCT-VIII are derived and implemented as accelerators of transform functions of the future video coding technology. The synthesis results show lower hardware costs and improved efficiency with respect to the reference implementations. The second technique relies on the steerable method, which is extended to design directional transforms starting from any two-dimensional separable transform. Then, the HEVC steerable integer DCT and DST are defined and integrated on the top of the standard. The simulations show coding efficiency gains when using transforms with different orientation. Finally, the application of steerable transforms to partial video encryption is also analyzed.
Transform algorithms and architectures for video coding / Masera, Maurizio. - (2018 May 31).
Transform algorithms and architectures for video coding
MASERA, MAURIZIO
2018
Abstract
During the last years, the increasing popularity of very high resolution formats and the growing of video applications have posed critical issues on both the coding efficiency and the complexity of video compression systems. This thesis focuses on the transform coding stage of the most recent video coding technologies, by addressing both the complexity evaluation and the design of custom hardware architectures. First, the thesis thoroughly analyzes the HEVC transform complexity, by relying on the proposed CI metric. A tool-by-tool investigation is performed to quantify the complexity of the transform stage as function of different coding options, thus identifying which parameters are mainly related to the quality-complexity trade-off. The analysis is concluded with the determination of the transform stage requirements for real life HEVC encoders working in real-time. The obtained results motivate the need of transform hardware architectures. Therefore, an exploration of alternative solutions for hardware architectures to compute the transforms required by the standard is provided. Different DCT and DST factorizations and approximations have been compared in terms of arithmetic cost and sharing degree between multiple transform sizes in order to select the best promising ones for hardware implementation. Then, 1D and 2D transform architectures are proposed and their performance are evaluated within HEVC. The rate-distortion analysis and the hardware synthesis show that the proposed DCT and DST architectures achieve significant area and power reduction with respect to the state-of-art implementations at the expense of very small coding efficiency loss. Finally, this thesis investigates some adaptive transform coding techniques for beyond HEVC video compression, which try to represent the signal with a more sparse representation. The first technique employs odd type sinusoidal transforms. Therefore, some relationships for odd type DCTs and DSTs are recalled and exploited to reuse known factorizations of the DCT-VI and DST-VII to obtain other odd type transforms by applying simple permutations and sign inversions. Low-complexity DCT-V and DCT-VIII are derived and implemented as accelerators of transform functions of the future video coding technology. The synthesis results show lower hardware costs and improved efficiency with respect to the reference implementations. The second technique relies on the steerable method, which is extended to design directional transforms starting from any two-dimensional separable transform. Then, the HEVC steerable integer DCT and DST are defined and integrated on the top of the standard. The simulations show coding efficiency gains when using transforms with different orientation. Finally, the application of steerable transforms to partial video encryption is also analyzed.Pubblicazioni consigliate
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https://hdl.handle.net/11583/2709432
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