A framework for low power and architectural design space exploration based on high-level synthesis

This thesis is an effort in the area of electronic design automation applied to system-level modeling of embedded systems using high-level synthesis (HLS). We have investigated two research areas. The first area of research is application oriented and targets the FPGA implementation of the Semi-Global Matching (SGM) algorithm for the stereo vision system, using high-level synthesis. We wanted to explore if such a design with moderate complexity was suitable for HLS or not. High-level synthesis offers several advantages over the traditional design flow start at the Register Transfer Level (RTL), such as faster simulation run-time and better design re-use, thanks to the higher level of abstraction. We also wanted to compare the quality of results, flexibility and design time that we achieved using both HLS and manual RTL design. The use of HLS is particularly promising because the automotive industry is very sensitive to production costs; hence it requires various implementations of the same algorithm, with very different resolutions, costs, and performance levels, for different target market segments. The second research activity presents a novel low-power design methodology based on HLS and targets the ASIC implementation flow. As far as functional description of hardware is concerned, it has evolved to the extent that model-based design approaches using automated HLS flows have gained popularity within the design community. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system level description. The process requires considerable amount of human intervention and various lower-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high level synthesis to achieve a broad set of target system implementations. LP-HLS uses set of pragmas and a directive file to derive power intent information. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology.