Robust and Efficient Globally-Asynchronous Locally-Synchronous (GALS) digital design

Process and operating condition variability creates a huge problem for current and future digital integrated circuits, because it forces them to operate at a speed, voltage and hence power and energy consumption which is very far from the optimum. System on Chip (SoC) architectures are born to meet some of the microelectronic trends. A single integrated chip contains an entire system with one or more central processors, several other chip-set, memories, and interfaces. The bottleneck of this approach are the interconnections between the various components. A global asynchronous communication is particularly suitable for this purpose because it removes most of the variable delays of the synchronous operation. At the same time, there is always the need to optimize the speed or power consumption of the computation and the Razor approach has been built for this purpose (trying to go below the synchronous safe operation). So the goal of my work was to implement a new Globally-Asynchronous Locally-Synchronous (GALS) architecture that combines Safe Razor modules connected by flexible asynchronous communication channels. In such architecture, both computation and communication are executed without the margins required by the synchronous worst-case methodology achieving better performance. The thesis makes two contributions to the state of the art: 1. Safe-Razor: a metastability-robust adaptive clocking inside each synchronous GALS module. 2. M-of-N PID code: an efficient Delay-Insensitive (DI) protocol for the asynchronous communication between the GALS modules.