The exponential growth of computing power that we have been used-to since years is about to face new challenges, most notably for technical and economical reasons. It is highly debated when it will be time to go past traditional CMOS technology, but from ITRS data we know that traditional ultra-deep submicron devices are approaching fundamental physical limits. From an economical point of view, the extremely high costs of chip masks and production plants are posing substantial limitations to the development margins. The end of a remarkably successful era in computing is approaching then. It’s the era where Moore’s Law reigns and processing power per dollar doubles every year. A new era, though, is on the horizon [52]: the nanoelectronics era, with ever smaller devices and higher densities, to keep up with pace. Among the envisaged solutions to these arising problems, alternatives to traditional computation have been proposed, in the form of numerous so-called disruptive nanotechnologies. Some of the proposals innovate also the technological approach, moving from the conventional top-down process to a chemical self-assembly process. None of these effort is mature to the point to substitute CMOS any time soon, but this is the right time to be deeply involved in their study and contribute to their progress towards the moment when some of these will provide a valid alternative. The risk, else, would be to miss not just the next evolutionary step, but a revolution in the approach to computation. The fact that a clear winner is far and away from being declared among the competitors stresses the need to study different technology proposals. The scaling of the featured size of devices in disruptive nanotechnologies also requires to deal with added complexity, that is the price to pay for a great density advantage. Many nanotechnologies, and for sure the ones based on chemical self-assembly, suffer from two problems. First, the self-assembly nature of the process renders almost impossible to replicate complex aperiodic structures, as in the CMOS case. Then, the thermodynamical nature of the assembly makes structures sensitive to temperature variations. To put it more simply, disruptive nanotechnologies suffer from greater defect rates with respect to CMOS. Fault-tolerance techniques must be applied to fabrics, irrespective to the architecture of choice. The net gain, we said, on one side is the prospected density advantage, estimated in up to three orders of magnitude with respect to the limits traced by IRTS, plus a ultra-low power consumption: these are among the main reasons driving computational research in the field in this direction. This doctoral work focuses on the need to address specific questions that apply to many disruptive nanotechnologies. • Is it possible to cope with high defect rates? • How to interconnect nanoscale devices or logic blocks? • Which architectures are best fit for these high density devices? These questions are just an exemplification of the many questions that researchers are trying to answer. In our view, there is a methodological problem that has to be solved first and foremost. The problem is about which approach is scientifically sound to get data to answer the aforementioned question. It is our believe that building analytical models first, to study different technologies, would lead to conclusions that could hardly be considered convincing. In [27] we showed how an analytical model, despite its intricacy, is far from close to model the complexity of the system it mimics, and so are the attained results. From a methodological point of view, then, we argue that numerical simulations are needed to tackle the great complexity of these systems, irrespective of technology at hand, and this requires CAD tools specifically designed to study the nascent problems of emerging technology. Unfortunately, to the best of our knowledge, no such tool was developed before this work. Why, then, we observed a tendency to exploit existing tools to cross the bridge between nanotechnologies and nanoarchitectures? Was this due to the fact that existing tools were good at solving the new challenges as well? This could hardly be the reason why. In fact, it is rather difficult, if possible, to put up a toolchain of existing softwares, able to provide a complete workflow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle nanotechnology-related constraints. This work focuses on the development of such a tool, ToPoliNano. The software functionalities are described in details, alongside with attained results. It has the ability, starting from a circuit by parsing its VHDL description, to target different disruptive nanotechnologies (different Nanoarray-based architectures [143] and NanoMagneticLogics (NML), also known as Magnetic QCA (M-QCA) [76] supported at present time), to place and route it on a floorplan and then simulate it, in an integrated fashion. The tool has been used to study specific architectures devised to exploit the power of emerging technologies. ToPoliNano tool covers a broad range of abstraction levels, from the device level, to the circuit level, up to the architectural level. It is then possible to draw conclusions at architectural level starting from modeling at device level. This is critical to trust architectural results, usually prone to huge errors. Massively parallel architectures were studied to exploit regularity of these fabrics; this approach seems more promising than massive data parallelism. Logic and timing simulations have been performed, and results published in International Journals and Conferences [25, 26, 27, 32, 65, 77]. The organization of this document is as follows. Part I consists in Chapter 1, which is introductory to the technologies handled by ToPoliNano, providing background and state-of-the art information on the subject. Part II opens with Chapter 2, which is about general organization of the application, providing an overview of the specifications and of the most advanced characteristics of the ToPoliNano software. Chapter 3 provides information about the software at two levels of detail: introductory, if the subject is further developed in other parts of the work, informative else. Chapter 4 deals with details of the VHDL parsing module. Chapter 5 deals with details of the Input Stimuli Generator, while Chapter 6 thoroughly details implementation and results of the Simulation Engine(s) of the software. In Chapter 7 a key component for ToPoliNano’s flexibility in dealing with different nanotechnologies is described: the Library Generator. Part II is closed by Chapter 8, in which a case study is presented, with an architecture proposal for biosequence analysis and simulation results.

Massively Parallel Nanoarchitectures: structures, algorithms and simulation tools / Frache, Stefano. - (2013).

Massively Parallel Nanoarchitectures: structures, algorithms and simulation tools

FRACHE, STEFANO
2013

Abstract

The exponential growth of computing power that we have been used-to since years is about to face new challenges, most notably for technical and economical reasons. It is highly debated when it will be time to go past traditional CMOS technology, but from ITRS data we know that traditional ultra-deep submicron devices are approaching fundamental physical limits. From an economical point of view, the extremely high costs of chip masks and production plants are posing substantial limitations to the development margins. The end of a remarkably successful era in computing is approaching then. It’s the era where Moore’s Law reigns and processing power per dollar doubles every year. A new era, though, is on the horizon [52]: the nanoelectronics era, with ever smaller devices and higher densities, to keep up with pace. Among the envisaged solutions to these arising problems, alternatives to traditional computation have been proposed, in the form of numerous so-called disruptive nanotechnologies. Some of the proposals innovate also the technological approach, moving from the conventional top-down process to a chemical self-assembly process. None of these effort is mature to the point to substitute CMOS any time soon, but this is the right time to be deeply involved in their study and contribute to their progress towards the moment when some of these will provide a valid alternative. The risk, else, would be to miss not just the next evolutionary step, but a revolution in the approach to computation. The fact that a clear winner is far and away from being declared among the competitors stresses the need to study different technology proposals. The scaling of the featured size of devices in disruptive nanotechnologies also requires to deal with added complexity, that is the price to pay for a great density advantage. Many nanotechnologies, and for sure the ones based on chemical self-assembly, suffer from two problems. First, the self-assembly nature of the process renders almost impossible to replicate complex aperiodic structures, as in the CMOS case. Then, the thermodynamical nature of the assembly makes structures sensitive to temperature variations. To put it more simply, disruptive nanotechnologies suffer from greater defect rates with respect to CMOS. Fault-tolerance techniques must be applied to fabrics, irrespective to the architecture of choice. The net gain, we said, on one side is the prospected density advantage, estimated in up to three orders of magnitude with respect to the limits traced by IRTS, plus a ultra-low power consumption: these are among the main reasons driving computational research in the field in this direction. This doctoral work focuses on the need to address specific questions that apply to many disruptive nanotechnologies. • Is it possible to cope with high defect rates? • How to interconnect nanoscale devices or logic blocks? • Which architectures are best fit for these high density devices? These questions are just an exemplification of the many questions that researchers are trying to answer. In our view, there is a methodological problem that has to be solved first and foremost. The problem is about which approach is scientifically sound to get data to answer the aforementioned question. It is our believe that building analytical models first, to study different technologies, would lead to conclusions that could hardly be considered convincing. In [27] we showed how an analytical model, despite its intricacy, is far from close to model the complexity of the system it mimics, and so are the attained results. From a methodological point of view, then, we argue that numerical simulations are needed to tackle the great complexity of these systems, irrespective of technology at hand, and this requires CAD tools specifically designed to study the nascent problems of emerging technology. Unfortunately, to the best of our knowledge, no such tool was developed before this work. Why, then, we observed a tendency to exploit existing tools to cross the bridge between nanotechnologies and nanoarchitectures? Was this due to the fact that existing tools were good at solving the new challenges as well? This could hardly be the reason why. In fact, it is rather difficult, if possible, to put up a toolchain of existing softwares, able to provide a complete workflow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle nanotechnology-related constraints. This work focuses on the development of such a tool, ToPoliNano. The software functionalities are described in details, alongside with attained results. It has the ability, starting from a circuit by parsing its VHDL description, to target different disruptive nanotechnologies (different Nanoarray-based architectures [143] and NanoMagneticLogics (NML), also known as Magnetic QCA (M-QCA) [76] supported at present time), to place and route it on a floorplan and then simulate it, in an integrated fashion. The tool has been used to study specific architectures devised to exploit the power of emerging technologies. ToPoliNano tool covers a broad range of abstraction levels, from the device level, to the circuit level, up to the architectural level. It is then possible to draw conclusions at architectural level starting from modeling at device level. This is critical to trust architectural results, usually prone to huge errors. Massively parallel architectures were studied to exploit regularity of these fabrics; this approach seems more promising than massive data parallelism. Logic and timing simulations have been performed, and results published in International Journals and Conferences [25, 26, 27, 32, 65, 77]. The organization of this document is as follows. Part I consists in Chapter 1, which is introductory to the technologies handled by ToPoliNano, providing background and state-of-the art information on the subject. Part II opens with Chapter 2, which is about general organization of the application, providing an overview of the specifications and of the most advanced characteristics of the ToPoliNano software. Chapter 3 provides information about the software at two levels of detail: introductory, if the subject is further developed in other parts of the work, informative else. Chapter 4 deals with details of the VHDL parsing module. Chapter 5 deals with details of the Input Stimuli Generator, while Chapter 6 thoroughly details implementation and results of the Simulation Engine(s) of the software. In Chapter 7 a key component for ToPoliNano’s flexibility in dealing with different nanotechnologies is described: the Library Generator. Part II is closed by Chapter 8, in which a case study is presented, with an architecture proposal for biosequence analysis and simulation results.
File in questo prodotto:
File Dimensione Formato  
TesiPhDFrache.pdf

non disponibili

Tipologia: 1. Preprint / submitted version [pre- review]
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 6.95 MB
Formato Adobe PDF
6.95 MB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2518616
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo