This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

N Point DCT VLSI Architecture for Emerging HEVC Standard / Ahmed, Ashfaq; Rehman, ATA UR; Shahid, MUHAMMAD USMAN. - In: VLSI DESIGN. - ISSN 1065-514X. - 2012:752024(2012), pp. 1-13. [10.1155/2012/752024]

N Point DCT VLSI Architecture for Emerging HEVC Standard

AHMED, ASHFAQ;REHMAN, ATA UR;SHAHID, MUHAMMAD USMAN
2012

Abstract

This work presents a flexible VLSI architecture to compute the N-point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2502043
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