2026-09-19T16:14:54Zhttps://iris.polito.it/oai/requestoai:iris.polito.it:11583/29832062025-04-09T00:04:16Zcom_11583_2614433com_11583_2614425col_11583_2614423
VLSI ARCHITECTURES FOR VIDEO PROCESSING AND RISC-V
WALID, WALID
Walid, Walid
MARTINA, MAURIZIO
MASERA, Guido
Discriminative correlation filter · DSST · Real time · FPGA · QR · SVD · DFT · HOG · Video Encoding · AV1 · Wiener filter · VLSI · RISC-V · ISA · Super-scalar · CPU · Out-of-Order
Settore ING-INF/01 - Elettronica
L'abstract è presente nell'allegato / the abstract is in the attachment
2023-10-09
info:eu-repo/semantics/doctoralThesis
https://hdl.handle.net/11583/2983206
eng
firstpage:1
lastpage:128
numberofpages:128
info:eu-repo/semantics/openAccess
Politecnico di Torino
country:Italy
license:Creative commons
license:Creative commons
license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/
license uri:http://creativecommons.org/licenses/by-nc-nd/4.0/