A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time- to-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 μm × 55 μm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders.

The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking / Piccolo, Lorenzo; Rivetti, Angelo; Cadeddu, Sandro; Casu, Luigi; Lai, Adriano; Barbaro, Massimo; Napoli, Corrado; Sonedda, Stefano; Frontini, Luca; Liberali, Valentino; Stabile, Alberto; Shojaii, Jafar. - ELETTRONICO. - (2020), p. 022. (Intervento presentato al convegno TWEPP 2019) [10.22323/1.370.0022].

The first ASIC prototype of a 28 nm time-space front-end electronics for real-time tracking

Piccolo, Lorenzo;
2020

Abstract

A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a time- to-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 μm × 55 μm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2846525