This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the N-point DCT by means of two N/2-point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware reusability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion losses, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel.

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding / Masera, M.; Masera, G.; Martina, M.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY. - ISSN 1051-8215. - STAMPA. - 30:1(2020), pp. 232-242. [10.1109/TCSVT.2018.2886736]

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding

Masera M.;Masera G.;Martina M.
2020

Abstract

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the N-point DCT by means of two N/2-point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware reusability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion losses, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel.
File in questo prodotto:
File Dimensione Formato  
published.pdf

non disponibili

Descrizione: Versione Pubblicata
Tipologia: 2a Post-print versione editoriale / Version of Record
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 2.41 MB
Formato Adobe PDF
2.41 MB Adobe PDF   Visualizza/Apri   Richiedi una copia
FINAL_VERSION_iris.pdf

accesso aperto

Descrizione: Versione Finale
Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 337.74 kB
Formato Adobe PDF
337.74 kB Adobe PDF Visualizza/Apri
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2778172