Development of low power front-end electronics for monolithic Active Pixel Sensors

The next generation High Energy Physics experiments require the development of novel radiation sensor technologies adequate to cover very large areas and suitable for extreme radiation conditions. In this field, thanks to its incomparable properties, silicon is still nowadays the dominant semiconductor used to build tracking detectors for ionizing particles. In several experiments all around the world, it is used to cover very large areas with the intent of tracking and identifying the crossing particles generated during the experiments. Different topologies of silicon sensors can be used for these applications but those commonly used for high rate environments are pixel sensors. This research activity focuses mainly on two particular types of these sensors: hybrid pixel sensors and monolithic active pixel sensors (MAPS). Modern detectors use intensively hybrid sensors due to their excellent properties. This technology indeed allows to develop sensor and electronics separately allowing a very effective optimization of each part of the device increasing in this way its versatility and allowing to meet most of the requirements of the new experiments. The hybrid technology is fast and also suitable for working in high radiation environments thanks to the use of high electrical fields for the charge collection. However, the production cost of those devices is much higher than other sensors because two different devices are required and also due to the additional cost for the bump bonding used to interconnect sensor and readout ASIC. On the other hand, monolithic sensors are based on the implementation of sensor and readout electronics in the same silicon wafer. Therefore this technology is much cheaper than the hybrid solution and allows to reduce significantly contribution of the detector to the material budget. However, traditional MAPS have some limitations in terms of speed, extension of the depletion volume, signal to noise ratio and radiation tolerance which make those devices unsuitable for the extreme environment of the new experiments. In this context, this work presents the development of a full depleted monolithic pixel sensor with a thickness of 300 μm which aims to overcome the main limitations of the conventional monolithics. The proposed device has properties similar to the hybrid solution but benefits of the low production cost typical of monolithics. The development of the device has been carried out by the collaboration between the University of Trento, INFN of Padova and INFN of Torino. In addition, thanks to the close collaboration with the experts of a silicon foundry, it was possible a tailored fabrication of the devices. Two ASICs of 2 mm × 2 mm have been developed in a customized double-sided CMOS technology with transistors of 1.2 V and 6 metal layers. The devices have been submitted to the foundry for fabrication on April 2016 and have been delivered for the testing phase on May 2017. A patent for the device has been granted in 2017. In the first part of this work, the state of the art of monolithics is given where hybrid and monolithics are compared. Then, the novel sensor is described in detail with the support of simulations to motivate important solutions adopted to reach the full depletion and to implement PMOS transistors avoiding the competitive charge collection. Some studies to highlight the huge limitations on design MAPS without access to the process data are presented to introduce the custom process used for the development of the device. The first ASIC is a test chip designed to contain test devices used to study important properties of the sensor like depletion and punch-through voltage. All the devices implemented in this ASIC are described in detail motivating the design solutions adopted. The second ASIC is the complete monolithic sensor called MATISSE (Monolithic AcTIve pixel SenSor Electronics) made by a matrix array of 24 × 24 pixels readout with the snapshot shutter technique. Each pixel is 50 μm×50 μm and is based on the same novel sensor. The chip is described in detail with the support of simulation results to motivate some strategies adopted during the design. Special emphasis is placed on the strategy used to design the readout chain with a wide output swing, low noise and excellent linearity with the use of high threshold transistors. Last but not least, in the last chapter the results collected during the characterization of the two prototypes for different wafers are presented. The data acquisition system developed is described and the electrical tests and measurements with active sources and lasers are reported. The measurements performed on the test structures show unwanted trapped charge in the backside oxide. The phenomenon is described putting special attention on an irradiation campaign performed in the test diodes to confirm and quantify this effect. All the results presented in this work aim to prove the device full depletion and the excellent properties of the embedded electronics implemented in these first prototypes.