Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis

Multi-processor system-on-chip (MPSoC) devices are a well known replacement of single-core devices. Some industries, like avionic, are particularly sensitive to the weight and power consumption. Such industries would really take advantage of reducing the number of computers by using MPSoCs. However, the usage of such devices in safety critical domain is currently more than limited. The main issue, which hinders the MPSoC usage in safety critical field, is the presence of on-chip resources shared by the cores. The interconnection itself is the most evident these shared resources. This aspect is an issue as it undermines the safety aspect of the system by providing non functional dependencies, especially from the timing point of view. The certification process is crucial in safety critical field and the system complexity makes the whole certification process harder and even unfeasible. The certification requires to prove that the system exhibits a precise set of guarantees to the safety-critical tasks. While the complexity was an issue for the well known bus-based MPSoCs, it becomes even more critical for the emerging network- on-chip (NoC) interconnection model. The QoSinNoC framework has been created to analyze a set of simple NoC architectures and the related techniques to enable their usage in the scope of mixed criticality. The main contribution of this work is an alternative routing algorithm which allows a better system utilization without any hardware modifications to the NoC architectures considered by QoSinNoC. Furthermore the framework has been upgraded with the power estimation feature which allows a better design space exploration.