Modern low power designs use multiple knobs for concurrent dynamic and leakage power optimization; supply voltage and threshold voltage are the most adopted. An efficient control of these knobs needs management policies aware of the power breakdown. This implies the availability of smart on-chip strategies for dynamic and leakage power estimation at runtime. In this paper, we address this issue proposing the implementation of embedded dynamic/static power meters that use an optimized regression model fed with data collected from in-situ activity monitors. The number of sensors, their bitwidth and optimal placement are obtained through an automated design flow. The methodology works for general logic and applies not just to processor cores, but also to application-specific designs. We apply our solution to a representative class of benchmarks, showing that it can achieve an average estimation error smaller than 3%, with limited area and power overheads.

All-digital embedded meters for on-line power estimation / Jahier Pagliari, Daniele; Peluso, Valentino; Chen, Yukai; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2018), pp. 737-742. (Intervento presentato al convegno 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) tenutosi a Dresden, Germany nel 19-23 March 2018) [10.23919/DATE.2018.8342105].

All-digital embedded meters for on-line power estimation

Jahier Pagliari, Daniele;Peluso, Valentino;Chen, Yukai;Calimera, Andrea;Macii, Enrico;Poncino, Massimo
2018

Abstract

Modern low power designs use multiple knobs for concurrent dynamic and leakage power optimization; supply voltage and threshold voltage are the most adopted. An efficient control of these knobs needs management policies aware of the power breakdown. This implies the availability of smart on-chip strategies for dynamic and leakage power estimation at runtime. In this paper, we address this issue proposing the implementation of embedded dynamic/static power meters that use an optimized regression model fed with data collected from in-situ activity monitors. The number of sensors, their bitwidth and optimal placement are obtained through an automated design flow. The methodology works for general logic and applies not just to processor cores, but also to application-specific designs. We apply our solution to a representative class of benchmarks, showing that it can achieve an average estimation error smaller than 3%, with limited area and power overheads.
2018
978-3-9819263-0-9
File in questo prodotto:
File Dimensione Formato  
895_OutputPaper.pdf

accesso aperto

Descrizione: Articolo principale
Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 254.74 kB
Formato Adobe PDF
254.74 kB Adobe PDF Visualizza/Apri
All-digital_embedded_meters_for_on-line_power_estimation.pdf

non disponibili

Descrizione: Articolo principale (versione editoriale)
Tipologia: 2a Post-print versione editoriale / Version of Record
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 185.63 kB
Formato Adobe PDF
185.63 kB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2709739