SRAM-based FPGAs are becoming increasingly suitable for avionic and space applications due to their flexibility, reconfigurability and capacity as well as their signal processing capabilities. Unfortunately, commercial-of-the-shelf (COTS) SRAM-based FPGAs are highly sensitive to ionizing radiation environment such as space or avionic, making them extremely sensitive to radiation-induced Single Event Upsets (SEUs). In this paper, we propose a detection solution able to detect SEU-effects before they affect the circuit functionalities. The developed solution overcome state-of-the-art techniques since it is able to anticipate the detection of SEU-effects with an improvement of the latency of more than 70% than traditional redundancy based mitigation techniques. Besides, the proposed solution has a negligible impact on the circuit timing, since it does not introduce any performance degradation and it has a limited cost in terms of area usage. Experimental results performed on three benchmark circuits with traditional Duplication with Comparison (DEC) error detection technique demonstrate the feasibility of the proposed method showing an improvement of the detection capability of around 98% on the average.

A probe-based SEU detection method for SRAM-based FPGAs / Sterpone, Luca; Boragno, Luca. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - ELETTRONICO. - 76-77C:(2017), pp. 154-158. [10.1016/j.microrel.2017.07.077]

A probe-based SEU detection method for SRAM-based FPGAs

STERPONE, LUCA;BORAGNO, LUCA
2017

Abstract

SRAM-based FPGAs are becoming increasingly suitable for avionic and space applications due to their flexibility, reconfigurability and capacity as well as their signal processing capabilities. Unfortunately, commercial-of-the-shelf (COTS) SRAM-based FPGAs are highly sensitive to ionizing radiation environment such as space or avionic, making them extremely sensitive to radiation-induced Single Event Upsets (SEUs). In this paper, we propose a detection solution able to detect SEU-effects before they affect the circuit functionalities. The developed solution overcome state-of-the-art techniques since it is able to anticipate the detection of SEU-effects with an improvement of the latency of more than 70% than traditional redundancy based mitigation techniques. Besides, the proposed solution has a negligible impact on the circuit timing, since it does not introduce any performance degradation and it has a limited cost in terms of area usage. Experimental results performed on three benchmark circuits with traditional Duplication with Comparison (DEC) error detection technique demonstrate the feasibility of the proposed method showing an improvement of the detection capability of around 98% on the average.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2680582
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo