Micro Latch-up Analysis on Ultra- Nanometer VLSI Technologies: A new Monte Carlo Approach

Ultra-scale devices based on technologies below 20nm are nowadays widely adopted due to their elevated computing features and low power consumption. These characteristics made them attractive even for fields where the high reliability is the major concern like automotive or aerospace ones. In order to guarantee a high reliability level, one of the major challenge in these application fields is the protection versus the micro latch-up effect: a phenomenon that temporarily affects the logical behavior of technology cells at various locations across the die provoking circuit misbehavior. In this paper, we propose a new analysis flow for detecting the occurrences of micro latch-up event considering the physical layout of a circuit. In details, a circuit layers has been developed in order to identify the micro latch-up sensitive points in the 3D layout geometry, while a Monte-Carlo approach has been developed to calculate the micro latch-up error rate on routing interconnection nodes. Experimental results have been performed by fault simulation on a benchmark circuit implemented in six different variants of routing congestion using a 15 nm COTS technology library demonstrating the feasibility of the proposed approach.