Aggressive feature-size scaling of silicon-based complementary metal-oxide semiconductor (CMOS) transistors is slowly approaching to its ultimate physical limitations. In an era where integrated circuits are supposed to be fast, reliable, and extremely power-efficient, worldwide scientists are striving to find an alternative material that could replace silicon in future electronic devices. During the past decade, graphene, a 2-D allotrope of carbon, has emerged as one of the most promising candidates. Mechanical strength and flexibility, combined with very high carrier mobility, make graphene a perfect material for the implementation of wearable devices. However, pristine graphene is a zero band-gap material, i.e., valence and conductance bands are touching each other near the Dirac points. The direct consequence is an insufficient ON/OFF current ratio that prevents graphene to implement the OFF-state. This poses severe limitations for digital applications, where a clear separation between 0- and 1-logic is fundamental. In this very historical period, most of the worldwide research on the topic is focused on finding practical methods to open the band-gap, in order to match, or at least approach, that of silicon. Available solutions like patterning, chemical doping, or combination with other materials, increase the level of disorder of graphene itself, with rather huge impact on its superlative pristine characteristics, e.g., reduced carrier mobility, in particular. Hence, the need of alternative, fine-tuned, techniques that best suite the mechanical and electrical properties of graphene, while preserving its intrinsic characteristics. The electrostatic doping principle falls in this category. It allows a fine-tuning of the Fermi Energy level in order to obtain equivalent p- or n-type graphene regions using an external electrical field applied through metal gates. Face to face regions with opposite doping profiles form an equivalent p-n junction, the key component behind any electronic circuit. The obtained graphene-based device is what we called Pass-XNOR (PX) gate, since its functionality resembles that of a transmission gate, but with an enhanced built-in logical Exclusive-NOR (XNOR) functionality. From a design-automation perspective, exploiting the expressive power of this new XNOR-based primitive sets a clear departure from classical abstraction models based on the And-Inverter representation, and manipulation, of Boolean logic functions. Therefore, new design methodologies are required to be developed. In this context, the contribution of this work is summarized as follows: (i) we propose a novel integration strategy for PX gates, called the Pass-XNOR Logic (PXL), that fruitfully exploits the built-in XNOR functionality of graphene p-n junctions in order to guarantee compact representations of rather complex Boolean logic functions; (ii) by resorting to the adiabatic charging principle, we demonstrate that PXL circuits are able to reach {\em deep-adiabatic} regimes with a performance improvement of several orders of magnitude w.r.t. silicon counterparts; (iii) we introduce a one-pass synthesis flow for PXL networks by means of a novel abstraction model, called the Pass Diagram, that allows to efficiently manipulate large Boolean networks built upon the XNOR primitive, as well as several synthesis and optimization algorithms which constitute the first CAD tool for graphene-based devices.

CAD Tools for Graphene-Based Electronic Circuits / Tenace, Valerio. - (2016).

CAD Tools for Graphene-Based Electronic Circuits

TENACE, VALERIO
2016

Abstract

Aggressive feature-size scaling of silicon-based complementary metal-oxide semiconductor (CMOS) transistors is slowly approaching to its ultimate physical limitations. In an era where integrated circuits are supposed to be fast, reliable, and extremely power-efficient, worldwide scientists are striving to find an alternative material that could replace silicon in future electronic devices. During the past decade, graphene, a 2-D allotrope of carbon, has emerged as one of the most promising candidates. Mechanical strength and flexibility, combined with very high carrier mobility, make graphene a perfect material for the implementation of wearable devices. However, pristine graphene is a zero band-gap material, i.e., valence and conductance bands are touching each other near the Dirac points. The direct consequence is an insufficient ON/OFF current ratio that prevents graphene to implement the OFF-state. This poses severe limitations for digital applications, where a clear separation between 0- and 1-logic is fundamental. In this very historical period, most of the worldwide research on the topic is focused on finding practical methods to open the band-gap, in order to match, or at least approach, that of silicon. Available solutions like patterning, chemical doping, or combination with other materials, increase the level of disorder of graphene itself, with rather huge impact on its superlative pristine characteristics, e.g., reduced carrier mobility, in particular. Hence, the need of alternative, fine-tuned, techniques that best suite the mechanical and electrical properties of graphene, while preserving its intrinsic characteristics. The electrostatic doping principle falls in this category. It allows a fine-tuning of the Fermi Energy level in order to obtain equivalent p- or n-type graphene regions using an external electrical field applied through metal gates. Face to face regions with opposite doping profiles form an equivalent p-n junction, the key component behind any electronic circuit. The obtained graphene-based device is what we called Pass-XNOR (PX) gate, since its functionality resembles that of a transmission gate, but with an enhanced built-in logical Exclusive-NOR (XNOR) functionality. From a design-automation perspective, exploiting the expressive power of this new XNOR-based primitive sets a clear departure from classical abstraction models based on the And-Inverter representation, and manipulation, of Boolean logic functions. Therefore, new design methodologies are required to be developed. In this context, the contribution of this work is summarized as follows: (i) we propose a novel integration strategy for PX gates, called the Pass-XNOR Logic (PXL), that fruitfully exploits the built-in XNOR functionality of graphene p-n junctions in order to guarantee compact representations of rather complex Boolean logic functions; (ii) by resorting to the adiabatic charging principle, we demonstrate that PXL circuits are able to reach {\em deep-adiabatic} regimes with a performance improvement of several orders of magnitude w.r.t. silicon counterparts; (iii) we introduce a one-pass synthesis flow for PXL networks by means of a novel abstraction model, called the Pass Diagram, that allows to efficiently manipulate large Boolean networks built upon the XNOR primitive, as well as several synthesis and optimization algorithms which constitute the first CAD tool for graphene-based devices.
2016
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2645325
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