A new EDA flow for the Mitigation of SEUs in Dynamic Reconfigurable FPGAs

This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial toolchain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average.