Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor.

On the functional test of L2 caches / Riga, M.; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - STAMPA. - (2012), pp. 84-90. (Intervento presentato al convegno 2012 IEEE 18th International On-line Testing Symposium (IOLTS)).

On the functional test of L2 caches

SANCHEZ SANCHEZ, EDGAR ERNESTO;SONZA REORDA, Matteo
2012

Abstract

Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor.
2012
9781467320832
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2498274
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