Power-gating has proved to be one of the most effective solutions for reducing stand-by leakage power in nanometer-scale CMOS circuits, and different strategies and algorithms for its application have been proposed recently. Unfortunately, power- gating comes with its own set of costs: Performance degradation, area increase, dynamic power increase and routing congestion. When a decision to power-gate a design has to be taken, pros and cons of power-gating have to be properly weighted to achieve optimal results. In this paper, we define "Figures of Merit" (FoMs) for power-gating, which can be used by designers to better understand the benefits and costs of power-gating, thereby allowing them to achieve optimal results. We then quantify the FoMs by applying a state-of-the-art, industry-strength power- gating flow on a set of designs implemented onto an industrial 65 nm CMOS process, and provide insightful discussion on how optimum power-gating can be achieved.

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; A., Pullini; L., Benini; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008). (Intervento presentato al convegno ISCAS 2008 tenutosi a Seattle, WA nel 18-21 May 2008) [10.1109/ISCAS.2008.4542029].

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

VISWESWARA SATHANUR, ASHOKA;CALIMERA, ANDREA;MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO
2008

Abstract

Power-gating has proved to be one of the most effective solutions for reducing stand-by leakage power in nanometer-scale CMOS circuits, and different strategies and algorithms for its application have been proposed recently. Unfortunately, power- gating comes with its own set of costs: Performance degradation, area increase, dynamic power increase and routing congestion. When a decision to power-gate a design has to be taken, pros and cons of power-gating have to be properly weighted to achieve optimal results. In this paper, we define "Figures of Merit" (FoMs) for power-gating, which can be used by designers to better understand the benefits and costs of power-gating, thereby allowing them to achieve optimal results. We then quantify the FoMs by applying a state-of-the-art, industry-strength power- gating flow on a set of designs implemented onto an industrial 65 nm CMOS process, and provide insightful discussion on how optimum power-gating can be achieved.
2008
9781424416837
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1856371
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