Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.

On-Line Instruction-checking in Pipelined Microprocessors / DI CARLO, Stefano; Di Natale, G.; Mariani, R.. - STAMPA. - (2008), pp. 377-382. (Intervento presentato al convegno IEEE 17th Asian Test Symposium (ATS) tenutosi a Sapporo, JP nel 24-27 Nov. 2008) [10.1109/ATS.2008.47].

On-Line Instruction-checking in Pipelined Microprocessors

DI CARLO, STEFANO;
2008

Abstract

Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.
2008
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1844480
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