Power maskable units have been proposed as a viable solution for preventing side-channel attacks to cryptoprocessors. This paper presents a novel architecture for the implementation of a class of such kinds of units, namely arithmetic components, which find wide usage in cryptographic applications and which are not suitable to traditional masking techniques. Results of extensive exploration and architectural trade-off analysis show the viability of the proposed solution.

A Novel Architecture for Power Maskable Arithmethic Units / Benini, L; Macii, Alberto; Macii, Enrico; Omerbegovic, E; Poncino, Massimo; Pro, F.. - (2003), pp. 136-140. (Intervento presentato al convegno GLS-VLSI-03: IEEE/ACM Great Lakes Symposium on VLSI, tenutosi a Washington, DC) [10.1145/764808.764].

A Novel Architecture for Power Maskable Arithmethic Units

MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO;
2003

Abstract

Power maskable units have been proposed as a viable solution for preventing side-channel attacks to cryptoprocessors. This paper presents a novel architecture for the implementation of a class of such kinds of units, namely arithmetic components, which find wide usage in cryptographic applications and which are not suitable to traditional masking techniques. Results of extensive exploration and architectural trade-off analysis show the viability of the proposed solution.
2003
1581136773
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500013
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo