The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits.

On applying the set covering model to reseeding / Chiusano, SILVIA ANNA; DI CARLO, Stefano; Prinetto, Paolo Ernesto; Wunderlich, H. J.. - STAMPA. - (2001), pp. 156-160. (Intervento presentato al convegno Design, Automation and Test in Europe, Conference and Exhibition (DATE) tenutosi a Munich, DE nel 13-16 March 2001) [10.1109/DATE.2001.915017].

On applying the set covering model to reseeding

CHIUSANO, SILVIA ANNA;DI CARLO, STEFANO;PRINETTO, Paolo Ernesto;
2001

Abstract

The Functional BIST approach is a rather new BIST technique based on exploiting embedded system functionality to generate deterministic test patterns during BIST. The approach takes advantages of two well-known testing techniques, the arithmetic BIST approach and the reseeding method. The main contribution of the present paper consists in formulating the problem of an optimal reseeding computation as an instance of the set covering problem. The proposed approach guarantees high flexibility, is applicable to different functional modules, and, in general, provides a more efficient test set encoding then previous techniques. In addition, the approach shorts the computation time and allows to better exploiting the tradeoff between area overhead and global test length as well as to deal with larger circuits.
2001
0769509932
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1416287
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