Archivio Istituzionale della RicercaComplex images represented through relational graphs can be recognized finding the isomorphic graph in a database of stored images. In this paper, the basic node of a processor array able promptly to verify the graph isomorphism is described. The internal architecture has been tuned on the algorithm behaviour and a first prototype containing four processors has been realized in the frame of the Eurochip program, using ES2 1-5 urn technology, while a successive version in ST 0-8 urn technology is currently being developed.
A VLSI processor array for graph isomorphism / Demarchi, Danilo; Masera, Guido; G., Piccinini. - In: INTERNATIONAL JOURNAL OF ELECTRONICS. - ISSN 0020-7217. - 76:4(1994), pp. 655-679. [10.1080/00207219408925962]
A VLSI processor array for graph isomorphism
DEMARCHI, DANILO;MASERA, Guido;
1994
Abstract
Complex images represented through relational graphs can be recognized finding the isomorphic graph in a database of stored images. In this paper, the basic node of a processor array able promptly to verify the graph isomorphism is described. The internal architecture has been tuned on the algorithm behaviour and a first prototype containing four processors has been realized in the frame of the Eurochip program, using ES2 1-5 urn technology, while a successive version in ST 0-8 urn technology is currently being developed.
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https://hdl.handle.net/11583/1403190
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