CARPEGNA, ALESSIO

CARPEGNA, ALESSIO  

Dipartimento di Automatica e Informatica  

091555  

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Citazione Data di pubblicazione Autori File
Spiking Neural Network Data Reduction via Interval Arithmetic / Saeedi, Sepide; Carpegna, Alessio; Savino, Alessandro; Di Carlo, Stefano. - ELETTRONICO. - (2022), pp. 1-6. (Intervento presentato al convegno The 18th IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE 2022) tenutosi a Virtual Event nel May 19 – May 20, 2022) [10.5281/zenodo.6581443]. 1-gen-2022 Saeedi, SepideCarpegna, AlessioSavino, AlessandroDi Carlo, Stefano Spiking Neural Network Data Reduction via Interval Arithmetic.pdf
Artificial Resilience in neuromorphic systems / Carpegna, Alessio; Di Carlo, Stefano; Savino, Alessandro. - ELETTRONICO. - (2022), pp. 1-3. (Intervento presentato al convegno International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) 2022 tenutosi a Tsukuba, Japan nel June 9-10, 2022) [10.1145/3535044.3535062]. 1-gen-2022 Carpegna, AlessioDi Carlo, StefanoSavino, Alessandro phDworkInProgress.pdfheart2022-18.pdf
Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic / Saeedi, Sepide; Carpegna, Alessio; Savino, Alessandro; Di Carlo, Stefano. - ELETTRONICO. - (2022), pp. 1-6. (Intervento presentato al convegno 23rd IEEE Latin-American Test Symposium (LATS 2022) tenutosi a Virtual Event nel 05-08 September 2022) [10.1109/LATS57337.2022.9936999]. 1-gen-2022 Saeedi, SepideCarpegna, AlessioSavino, AlessandroDi Carlo, Stefano Paper___LATS22___IA_NN_Model.pdfPrediction_of_the_Impact_of_Approximate_Computing_on_Spiking_Neural_Networks_via_Interval_Arithmetic.pdf
Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks / Carpegna, Alessio; Savino, Alessandro; Di Carlo, Stefano. - ELETTRONICO. - (2022), pp. 14-19. (Intervento presentato al convegno 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) tenutosi a Pafos, Cyprus nel 04-06 July 2022) [10.1109/ISVLSI54635.2022.00016]. 1-gen-2022 Carpegna, AlessioSavino, AlessandroDi Carlo, Stefano main.pdfSpiker_an_FPGA-optimized_Hardware_accelerator_for_Spiking_Neural_Networks.pdf
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS / Pavanello, F; Marchand, C; O'Connor, I; Orobtchouk, R; Mandorlo, F; Letartre, X; Cueff, S; Vatajelu, Ei; Di Natale, G; Cluzel, B; Coillet, A; Charbonnier, B; Noc, P; Kavan, F; Zoldak, M; Szaj, M; Bienstman, P; Van Vaerenbergh, T; Ruhrmair, U; Flores, P; Silva, Lge; Chaves, R; Silveira, Lm; Ceccatom, M; Gizopoulos, D; Papadimitrioull, G; Karakostas, V; Brando, A; Cazorla, Fj; Canal, R; Closas, P; Gusi-Amigo, A; Crovetti, P; Carpegna, A; Carmona, Tm; Di Carlo, S; Savino, A. - ELETTRONICO. - (2023), pp. 1-6. (Intervento presentato al convegno 2023 IEEE European Test Symposium (ETS) tenutosi a Venezia (ITA) nel 22-26 May 2023) [10.1109/ETS56758.2023.10173974]. 1-gen-2023 Crovetti, PCarpegna, ADi Carlo, SSavino, A + NEUROPULS_NEUROmorphic_energy-efficient_secure_accelerators_based_on_Phase_change_materials_aUgmented_siLicon_photonicS.pdfETC23-Neuropuls.pdf
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies / Pavanello, Fabio; Ioana Vatajelu, Elena; Bosio, Alberto; Van Vaerenbergh, Thomas; Bienstman, Peter; Charbonnier, Benoit; Carpegna, Alessio; DI CARLO, Stefano; Savino, Alessandro. - ELETTRONICO. - (2023), pp. 1-10. (Intervento presentato al convegno 41st IEEE VLSI Test Symposium tenutosi a San Diego CA (USA) nel 24-26 April 2023) [10.1109/vts56346.2023.10139932]. 1-gen-2023 Alessio CarpegnaStefano Di CarloAlessandro Savino + Special_Session_Neuromorphic_hardware_design_and_reliability_from_traditional_CMOS_to_emerging_technologies.pdfVTS23-Neuropuls.pdf
Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study / Kasap, Deniz; Carpegna, Alessio; Savino, Alessandro; DI CARLO, Stefano. - ELETTRONICO. - (2023), pp. 1-5. (Intervento presentato al convegno 2023 IEEE European Test Symposium (ETS) tenutosi a Venezia (ITA) nel 22-26 May 2023) [10.1109/ets56758.2023.10174219]. 1-gen-2023 Alessio CarpegnaAlessandro SavinoStefano Di Carlo + Micro-Architectural_features_as_soft-error_markers_in_embedded_safety-critical_systems_preliminary_study (1).pdfETS23-Microarch.pdf