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A Low-cost Emulation System for Fast Co-verification and Debug
2011 LAGOS BENITES, JORGE LUIS; Grosso, Michelangelo; Sterpone, Luca; SONZA REORDA, Matteo; Audisio, G.; Pipponzi, M.; Sabatini, M.
An FPGA-emulation-based platform for characterization of digital baseband communication systems
2011 LAGOS BENITES, JORGE LUIS; Grosso, Michelangelo; SONZA REORDA, Matteo; Audisio, G.; Pipponzi, M.; Sabatini, M.; Avantaggiati, V. A.
Worst Case-Induced Disturbances in Microstrip Interchip Interconnects by an External Electromagnetic Plane Wave - Part II: Analysis and Validation
2011 LAGOS BENITES, JORGE LUIS; Fiori, Franco
Worst-Case Induced Disturbances in Digital and Analog Interchip Interconnects by an External Electromagnetic Plane Wave - Part I: Modeling and Algorithm
2011 LAGOS BENITES, JORGE LUIS; Fiori, Franco
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Low-cost Emulation System for Fast Co-verification and Debug / LAGOS BENITES, JORGE LUIS; Grosso, Michelangelo; Sterpone, Luca; SONZA REORDA, Matteo; Audisio, G.; Pipponzi, M.; Sabatini, M.. - (2011), pp. 212-212. (Intervento presentato al convegno IEEE European Test Symposium tenutosi a Trondheim (N) nel May 23-27, 2011) [10.1109/ETS.2011.32]. | 1-gen-2011 | LAGOS BENITES, JORGE LUISGROSSO, MICHELANGELOSTERPONE, LucaSONZA REORDA, Matteo + | 2413925-mod.pdf |
| An FPGA-emulation-based platform for characterization of digital baseband communication systems / LAGOS BENITES, JORGE LUIS; Grosso, Michelangelo; SONZA REORDA, Matteo; Audisio, G.; Pipponzi, M.; Sabatini, M.; Avantaggiati, V. A.. - (2011), pp. 391-398. (Intervento presentato al convegno International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems tenutosi a Vancouver, B.C. (CA) nel Oct. 3-5, 2011) [10.1109/DFT.2011.1]. | 1-gen-2011 | LAGOS BENITES, JORGE LUISGROSSO, MICHELANGELOSONZA REORDA, Matteo + | 2443375-mod.pdf |
| Worst Case-Induced Disturbances in Microstrip Interchip Interconnects by an External Electromagnetic Plane Wave - Part II: Analysis and Validation / LAGOS BENITES, JORGE LUIS; Fiori, Franco. - In: IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY. - ISSN 0018-9375. - STAMPA. - 53:2(2011), pp. 491-500. [10.1109/TEMC.2010.2089566] | 1-gen-2011 | LAGOS BENITES, JORGE LUISFIORI, Franco | - |
| Worst-Case Induced Disturbances in Digital and Analog Interchip Interconnects by an External Electromagnetic Plane Wave - Part I: Modeling and Algorithm / LAGOS BENITES, JORGE LUIS; Fiori, Franco. - In: IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY. - ISSN 0018-9375. - STAMPA. - 53:1(2011), pp. 178-184. [10.1109/TEMC.2010.2085005] | 1-gen-2011 | LAGOS BENITES, JORGE LUISFIORI, Franco | - |