Archivio Istituzionale della RicercaSfoglia per Autore
Exploring the Impact of Architectural Parameters on Energy Efficiency of Application-Specific Block-Enabled SRAMs
2005 Sithambaram, P; Macii, Alberto; Macii, Enrico
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs
2005 Sithambaram, P.; Macii, Alberto; Macii, Enrico
Low-Overhead State-Retaining Elements for Low-Leakage MTCMOS Design
2005 Babighian, P; Benini, L; Macii, Alberto; Macii, Enrico
Evaluating regularity extraction in logic synthesis
2005 Chakraborty, A; Macii, Alberto; Macii, Enrico; Poncino, Massimo; Pandini, D.
PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI
2006 Macii, Alberto; Macii, E; Poncino, M; Squillero, Giovanni
Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion
2006 Babighian, P; Benini, L; Macii, Alberto; Macii, Enrico
Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology
2006 Chakraborty, A; Sithambaram, P; Duraisami, Karthik; Poncino, Massimo; Macii, Alberto; Macii, Enrico
Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits
2006 Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers
2006 Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective
2006 Ashutosh, Chakraborty; Duraisami, Karthik; VISWESWARA SATHANUR, A.; Prassanna, Sithambaram; Macii, Alberto; Macii, Enrico; Poncino, Massimo
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses
2007 Sithambaram, P.; Macii, Alberto; Macii, Enrico
Timing-driven row-based power gating
2007 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew
2007 Duraisami, Karthik; Sithambaram, P; Sathanur, A; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing
2007 VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
2007 Calimera, Andrea; Macii, Alberto; Pullini, A.; VISWESWARA SATHANUR, Ashoka; Benini, L.; Macii, Enrico; Poncino, Massimo
A Scalable Algorithmic Framework for Row-Based Power-Gating
2008 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
2008 Sathanur, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
2008 Macii, Alberto; Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Enrico; Poncino, Massimo
Dynamic thermal clock skew compensation using tunable delay buffers
2008 Chakraborty, A.; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P.; Macii, Alberto; Macii, Enrico; Poncino, Massimo
Optimal sleep transistor synthesis under timing and area constraints
2008 VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Exploring the Impact of Architectural Parameters on Energy Efficiency of Application-Specific Block-Enabled SRAMs / Sithambaram, P; Macii, Alberto; Macii, Enrico. - (2005), pp. 377-380. (Intervento presentato al convegno GLS-VLSI-05: ACM/IEEE Great Lakes Symposium on VLSI tenutosi a Chicago, Illinois) [10.1145/1057661.1057751]. | 1-gen-2005 | MACII, AlbertoMACII, Enrico + | - |
| Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs / Sithambaram, P.; Macii, Alberto; Macii, Enrico. - 3728:(2005), pp. 477-487. (Intervento presentato al convegno 15th International Workshop, PATMOS 2005 tenutosi a Leuven (BEL) nel September 21-23, 2005) [10.1007/11556930_49]. | 1-gen-2005 | MACII, AlbertoMACII, Enrico + | - |
| Low-Overhead State-Retaining Elements for Low-Leakage MTCMOS Design / Babighian, P; Benini, L; Macii, Alberto; Macii, Enrico. - (2005), pp. 367-370. (Intervento presentato al convegno GLS-VLSI-05: ACM/IEEE Great Lakes Symposium on VLSI tenutosi a Chicago, Illinois) [10.1145/1057661.1057749]. | 1-gen-2005 | MACII, AlbertoMACII, Enrico + | - |
| Evaluating regularity extraction in logic synthesis / Chakraborty, A; Macii, Alberto; Macii, Enrico; Poncino, Massimo; Pandini, D.. - 2:(2005), pp. 641-644. (Intervento presentato al convegno ISSCS 2005: International Symposium on Signals, Circuits and Systems, 2005. tenutosi a Iasi, Romania nel Luglio 2005) [10.1109/ISSCS.2005.1511322]. | 1-gen-2005 | MACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| PROGRAMMARE IN C: TEORIA, ESEMPI ED ESERCIZI SVOLTI / Macii, Alberto; Macii, E; Poncino, M; Squillero, Giovanni. - (2006). | 1-gen-2006 | MACII, AlbertoMACII EPONCINO MSQUILLERO, Giovanni | - |
| Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion / Babighian, P; Benini, L; Macii, Alberto; Macii, Enrico. - 1:(2006), pp. 126-131. (Intervento presentato al convegno DATE '06: Design, Automation and Test in Europe, 2006. tenutosi a Monaco di Baviera nel Marzo 2006) [10.1109/DATE.2006.243770]. | 1-gen-2006 | MACII, AlbertoMACII, Enrico + | - |
| Thermal Resilient Bounded-Skew Clock-Tree Optimization Methodology / Chakraborty, A; Sithambaram, P; Duraisami, Karthik; Poncino, Massimo; Macii, Alberto; Macii, Enrico. - (2006), pp. 832-837. (Intervento presentato al convegno DATE-06: IEEE Design Automation and Test in Europe tenutosi a Munich, Germany) [10.1109/DATE.2006.243740]. | 1-gen-2006 | DURAISAMI, KARTHIKPONCINO, MASSIMOMACII, AlbertoMACII, Enrico + | - |
| Implications of Ultra Low-Voltage Devices on Design Techniques for Controlling Leakage in NanoCMOS Circuits / Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 33-36. (Intervento presentato al convegno ISCAS-06: IEEE International Conference on Circuits and Systems tenutosi a Kos Island, Greece) [10.1109/ISCAS.2006.1692515]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers / Chakraborty, A; Duraisami, Karthik; Sithambaram, P; VISWESWARA SATHANUR, Ashoka; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 162-167. (Intervento presentato al convegno ISLPED-06: ACM/IEEE International Symposium on Low Power Electronics and Design tenutosi a Tegernsee, Germany) [10.1109/LPE.2006.4271829]. | 1-gen-2006 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective / Ashutosh, Chakraborty; Duraisami, Karthik; VISWESWARA SATHANUR, A.; Prassanna, Sithambaram; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2006), pp. 214-224. (Intervento presentato al convegno PATMOS-06: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation tenutosi a Montpellier, France) [10.1007/11847083_21]. | 1-gen-2006 | DURAISAMI, KARTHIKMACII, AlbertoENRICO MACIIPONCINO, MASSIMO + | - |
| New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses / Sithambaram, P.; Macii, Alberto; Macii, Enrico. - 4644:(2007), pp. 232-241. [10.1007/978-3-540-74442-9_23] | 1-gen-2007 | MACII, AlbertoMACII, Enrico + | - |
| Timing-driven row-based power gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 104-109. (Intervento presentato al convegno ISLPED-07: ACM/IEEE International Symposium on Low PowerElectronics and Design tenutosi a Portland, Oregon nel Agosto 2007) [10.1145/1283780.1283803]. | 1-gen-2007 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew / Duraisami, Karthik; Sithambaram, P; Sathanur, A; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 1061-1064. (Intervento presentato al convegno ISCAS-07: IEEE International Conference on Circuits and Systems tenutosi a New Orleans, Louisiana nel 27-30 May 2007) [10.1109/ISCAS.2007.378192]. | 1-gen-2007 | DURAISAMI, KARTHIKMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing / VISWESWARA SATHANUR, Ashoka; Calimera, Andrea; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2007), pp. 1-6. (Intervento presentato al convegno DATE-07: IEEE Design Automation and Test in Europe tenutosi a Nizza, Francia nel 16-20 April 2007) [10.1109/DATE.2007.364520]. | 1-gen-2007 | VISWESWARA SATHANUR, ASHOKACALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology / Calimera, Andrea; Macii, Alberto; Pullini, A.; VISWESWARA SATHANUR, Ashoka; Benini, L.; Macii, Enrico; Poncino, Massimo. - (2007), pp. 501-504. (Intervento presentato al convegno GLSVLSI-07: ACM/IEEE 17th Great Lakes Symposium on VLSI tenutosi a Stresa nel Marzo) [10.1145/1228784.1228903]. | 1-gen-2007 | CALIMERA, ANDREAMACII, AlbertoVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + | - |
| A Scalable Algorithmic Framework for Row-Based Power-Gating / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 379-384. (Intervento presentato al convegno DATE '08. Design, Automation and Test in Europe tenutosi a Munich (DEU) nel 10-14 March 2008) [10.1109/DATE.2008.4484710]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating / Sathanur, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 42-51. (Intervento presentato al convegno PATMOS-08: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation tenutosi a Lisboa, Portugal nel September 2008) [10.1007/978-3-540-95948-9_5]. | 1-gen-2008 | MACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Implementation of a thermal management unit for canceling temperature-dependent clock skew variations / Macii, Alberto; Chakraborty, A; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; Macii, Enrico; Poncino, Massimo. - In: INTEGRATION. - ISSN 0167-9260. - 41:1(2008), pp. 2-8. [10.1016/j.vlsi.2007.03.002] | 1-gen-2008 | MACII, AlbertoDURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, EnricoPONCINO, MASSIMO + | - |
| Dynamic thermal clock skew compensation using tunable delay buffers / Chakraborty, A.; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P.; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 16:6(2008), pp. 639-649. [10.1109/TVLSI.2008.2000248] | 1-gen-2008 | DURAISAMI, KARTHIKVISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
| Optimal sleep transistor synthesis under timing and area constraints / VISWESWARA SATHANUR, Ashoka; Pullini, A; Benini, L; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2008), pp. 177-182. (Intervento presentato al convegno GLSVLSI '08: 18th ACM Great Lakes symposium on VLSI tenutosi a Orlando, Florida nel May 04-06, 2008) [10.1145/1366110.1366155]. | 1-gen-2008 | VISWESWARA SATHANUR, ASHOKAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO + | - |
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