Sfoglia per Autore
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
2004 Violante, Massimo; Sterpone, Luca; M., Ceschia; D., Bortolato; Bernardi, Paolo; SONZA REORDA, Matteo; A., Paccagnella
On the evaluation of SEU sensitiveness in SRAM-based FPGAs
2004 Bernardi, Paolo; SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo
An experimental analysis of hardening techniques for SRAM-based FPGAs
2005 Sterpone, Luca; Violante, Massimo; S., Rezgui
An experimental analysis of hardening techniques for SRAM-based FPGAs
2005 Sterpone, Luca; Rezgui, S; Violante, Massimo
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
2005 Sterpone, Luca; Violante, Massimo
New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
2005 SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, Matteo; Squillero, Giovanni; Sterpone, Luca; Violante, Massimo
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
2005 SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo
A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
2005 Sterpone, Luca; Violante, Massimo
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
2005 F., Kastensmidt; Sterpone, Luca; SONZA REORDA, Matteo; L., Carro
A design flow for protecting FPGA-based systems against single event upsets
2005 Sterpone, Luca; Violante, Massimo
RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
2005 Sterpone, Luca; SONZA REORDA, Matteo; Violante, Massimo
A Fault Injection Environment for SoPC's Embedded Microprocessors
2006 M., PORTELA GARCIA; Sterpone, Luca; C., LOPEZ ONGIL; SONZA REORDA, Matteo; Violante, Massimo
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices
2006 Sterpone, Luca; Violante, Massimo
A new approach to compress the configuration information of programmable devices
2006 Martina, Maurizio; Masera, Guido; Molino, Andrea; Vacca, Fabrizio; Sterpone, Luca; Violante, Massimo
Combined software and hardware techniques for the design of reliable IP processors
2006 Rebaudengo, Maurizio; Sterpone, Luca; Violante, Massimo; C., Bolchini; A., Miele; D., Sciuto
An Experimental Analysis of a New Mixed Grain-Based Dynamically Reconfigurable Architecture
2006 Sterpone, Luca
ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
2006 Sterpone, Luca; Violante, Massimo
An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
2006 Sterpone, Luca; Violante, Massimo; S., Rezgui
Fault Injection-based Reliability Evaluation of SoPCs
2006 SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo; M., PORTELA GARCIA; C., LOPEZ ONGIL; L., Entrena
Hardening FPGA-based systems against SEUs: A new design methodology
2006 Sterpone, Luca; Violante, Massimo
Citazione | Data di pubblicazione | Autori | File |
---|---|---|---|
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs / Violante, Massimo; Sterpone, Luca; M., Ceschia; D., Bortolato; Bernardi, Paolo; SONZA REORDA, Matteo; A., Paccagnella. - In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE. - ISSN 0018-9499. - Volume: 51 , Issue: 6 , Part: 2:(2004), pp. 3354-3359. [10.1109/TNS.2004.839516] | 1-gen-2004 | VIOLANTE, MASSIMOSTERPONE, LucaBERNARDI, PAOLOSONZA REORDA, Matteo + | - |
On the evaluation of SEU sensitiveness in SRAM-based FPGAs / Bernardi, Paolo; SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo. - (2004), pp. 115-120. (Intervento presentato al convegno IEEE International On-Line Testing Symposium). | 1-gen-2004 | BERNARDI, PAOLOSONZA REORDA, MatteoSTERPONE, LucaVIOLANTE, MASSIMO | - |
An experimental analysis of hardening techniques for SRAM-based FPGAs / Sterpone, Luca; Violante, Massimo; S., Rezgui. - (2005), pp. J5-1-J5-4. (Intervento presentato al convegno RADECS). | 1-gen-2005 | STERPONE, LucaVIOLANTE, MASSIMO + | - |
An experimental analysis of hardening techniques for SRAM-based FPGAs / Sterpone, Luca; Rezgui, S; Violante, Massimo. - (2005). (Intervento presentato al convegno Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on) [10.1109/RADECS.2005.4365639]. | 1-gen-2005 | STERPONE, LucaVIOLANTE, MASSIMO + | - |
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs / Sterpone, Luca; Violante, Massimo. - In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE. - ISSN 0018-9499. - STAMPA. - 52:5(2005), pp. 1545-1549. [10.1109/TNS.2005.856543] | 1-gen-2005 | STERPONE, LucaVIOLANTE, MASSIMO | - |
New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores / SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, Matteo; Squillero, Giovanni; Sterpone, Luca; Violante, Massimo. - (2005), pp. 2193-2194. (Intervento presentato al convegno Genetic and Evolutionary Computation Conference) [10.1145/1068009.1068370]. | 1-gen-2005 | SANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSONZA REORDA, MatteoSQUILLERO, GiovanniSTERPONE, LucaVIOLANTE, MASSIMO | - |
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution / SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo. - (2005), pp. 136-141. (Intervento presentato al convegno IEEE European Test Symposium) [10.1109/ETS.2005.29]. | 1-gen-2005 | SONZA REORDA, MatteoSTERPONE, LucaVIOLANTE, MASSIMO | - |
A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs / Sterpone, Luca; Violante, Massimo. - In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE. - ISSN 0018-9499. - STAMPA. - 52:6(2005), pp. 2217-2223. [10.1109/TNS.2005.860745] | 1-gen-2005 | STERPONE, LucaVIOLANTE, MASSIMO | - |
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs / F., Kastensmidt; Sterpone, Luca; SONZA REORDA, Matteo; L., Carro. - 2:(2005), pp. 1290-1295. (Intervento presentato al convegno IEEE Design, Automation and Test in Europe tenutosi a Munich (Germany)) [10.1109/DATE.2005.229]. | 1-gen-2005 | STERPONE, LucaSONZA REORDA, Matteo + | - |
A design flow for protecting FPGA-based systems against single event upsets / Sterpone, Luca; Violante, Massimo. - (2005), pp. 436-444. (Intervento presentato al convegno IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems) [10.1109/DFTVS.2005.5]. | 1-gen-2005 | STERPONE, LucaVIOLANTE, MASSIMO | - |
RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs / Sterpone, Luca; SONZA REORDA, Matteo; Violante, Massimo. - 1:(2005), pp. 173-176. [10.1109/RME.2005.1543031] | 1-gen-2005 | STERPONE, LucaSONZA REORDA, MatteoVIOLANTE, MASSIMO | - |
A Fault Injection Environment for SoPC's Embedded Microprocessors / M., PORTELA GARCIA; Sterpone, Luca; C., LOPEZ ONGIL; SONZA REORDA, Matteo; Violante, Massimo. - (2006), pp. 68-73. (Intervento presentato al convegno 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina). | 1-gen-2006 | STERPONE, LucaSONZA REORDA, MatteoVIOLANTE, MASSIMO + | - |
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices / Sterpone, Luca; Violante, Massimo. - 1:(2006), pp. 189-190. [10.1109/IOLTS.2006.20] | 1-gen-2006 | STERPONE, LucaVIOLANTE, MASSIMO | - |
A new approach to compress the configuration information of programmable devices / Martina, Maurizio; Masera, Guido; Molino, Andrea; Vacca, Fabrizio; Sterpone, Luca; Violante, Massimo. - STAMPA. - 2:(2006), pp. 1289-1293. (Intervento presentato al convegno DATE tenutosi a Monaco di Baviera nel 6-10 marzo 2006) [10.1109/DATE.2006.243747]. | 1-gen-2006 | MARTINA, MAURIZIOMASERA, GuidoMOLINO, ANDREAVACCA, FABRIZIOSTERPONE, LucaVIOLANTE, MASSIMO | - |
Combined software and hardware techniques for the design of reliable IP processors / Rebaudengo, Maurizio; Sterpone, Luca; Violante, Massimo; C., Bolchini; A., Miele; D., Sciuto. - (2006), pp. 265-273. (Intervento presentato al convegno 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems) [10.1109/DFT.2006.18]. | 1-gen-2006 | REBAUDENGO, MaurizioSTERPONE, LucaVIOLANTE, MASSIMO + | - |
An Experimental Analysis of a New Mixed Grain-Based Dynamically Reconfigurable Architecture / Sterpone, Luca. - (2006), pp. 152-155. (Intervento presentato al convegno 13th IEEE International Conference on Electronics, Circuits and Systems). | 1-gen-2006 | STERPONE, Luca | - |
ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications / Sterpone, Luca; Violante, Massimo. - (2006), pp. 54-58. (Intervento presentato al convegno IEEE Workshop Design and Diagnostic of Electronic circuits and systems) [10.1109/DDECS.2006.1649570]. | 1-gen-2006 | STERPONE, LucaVIOLANTE, MASSIMO | - |
An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs / Sterpone, Luca; Violante, Massimo; S., Rezgui. - In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE. - ISSN 0018-9499. - (2006), pp. 2054-2059. [10.1109/TNS.2006.880937] | 1-gen-2006 | STERPONE, LucaVIOLANTE, MASSIMO + | - |
Fault Injection-based Reliability Evaluation of SoPCs / SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo; M., PORTELA GARCIA; C., LOPEZ ONGIL; L., Entrena. - 1:(2006), pp. 75-82. (Intervento presentato al convegno IEEE European Test Symposium) [10.1109/ETS.2006.24]. | 1-gen-2006 | SONZA REORDA, MatteoSTERPONE, LucaVIOLANTE, MASSIMO + | - |
Hardening FPGA-based systems against SEUs: A new design methodology / Sterpone, Luca; Violante, Massimo. - In: JOURNAL OF COMPUTERS. - ISSN 1796-203X. - 1:(2006), pp. 22-30. | 1-gen-2006 | STERPONE, LucaVIOLANTE, MASSIMO | - |
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